What happens when a GPU reads memory
This article provides a deep-dive technical analysis of how an NVIDIA RTX 4090 GPU processes memory load instructions at the hardware level. It traces the path of a global load instruction from the warp through the L1/L2 caches to DRAM.
Why it matters
Understanding low-level GPU memory architecture is critical for developers optimizing high-performance computing and AI workloads.
What happens when a GPU reads memory Fergus Finn Founder & Member of Technical Staff, Doubleword Contents From the warp to the L1 cache Entering the L1 cache Looking for L2: translation Lost in L2 Found in DRAM How the DRAM replies The way back Appendix: the probes Setup The L1 set function Page tables and the TLB The L2 slice function The L2 set index and geometry DRAM refresh Footnotes Our previous post followed a vector-add kernel — c[i] = a[i] + b[i] , one thread per float — from nvcc down to the warps. We went into a lot of detail on how the kernel was launched, but we also left a lot out.
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