High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders
Researchers at the Vellore Institute of Technology have developed a high-speed FPGA architecture for sine and cosine generation using the CORDIC algorithm. The design utilizes hybrid carry look-ahead adders to improve computational efficiency and reduce power consumption.
Why it matters
Advances in hardware architecture are critical for optimizing performance in embedded systems and digital signal processing applications.
Scientific Reports ( 2026 ) Cite this article
We’re sharing this article early to provide faster access to peer-reviewed, accepted research. It is citable and carries a permanent DOI. This version is subject to further edits and will be replaced automatically by the final Version of Record. All legal disclaimers apply.
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