Assembly Hall of Shame
This article explores the "Assembly Hall of Shame," a project dedicated to finding the absolute slowest single-instruction performance on x86 architecture, rather than optimizing for speed. It details strategies for instructions like `fxrstor64` and `nop` to achieve extremely high latency by exploiting memory access patterns and system contention. The goal is to push the boundaries of how long a single CPU instruction can be made to take.
Why it matters
This highly technical exploration provides insights into the intricate workings and potential bottlenecks of CPU architecture, which can be valuable for low-level system programmers, security researchers, or those interested in extreme performance analysis. It highlights how seemingly simple operations can be manipulated to consume vast amounts of CPU cycles, potentially revealing vulnerabilities or design quirks.
Instruction latency analysis usually focuses on performance optimization —making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.
x86 : fxrstor64 Strategy : Use fxrstor64 to load 512-byte FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric, then starve the fabric while the load is in flight — a fleet of hammer cores pounds a different high-latency MMIO register with tight 4-byte reads, saturating the PCIe root complex and endpoint with non-posted transactions, so CPU 0's 512-byte fxrstor64 must queue behind all that contending traffic.
; CPU 0 — timed instruction movl $ 0xfcc68830 , % rsi fxrstor64 % rsi ; CPUs 1..N — hammer loop against a different high-latency location movl 0xfcc68858 , % eax 🏆 Score : 198,002,498,236 cycles
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